1. Field of the Invention
The present invention relates generally to non-volatile semiconductor memory devices, and more particularly, to non-volatile semiconductor memory devices allowing exclusive erasing of storage data of a desired memory cell.
2. Description of the Background Art
Non-volatile semiconductor memory devices, differently from volatile semiconductor memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Type Random Access Memory), are characterized in that storage data is maintained after power is lost. PROM (Programmable Read Only Memory) is a representative of such non-volatile semiconductor memory devices. PROM is a non-volatile semiconductor memory device allowing users to write information therein. Typical of such PROM which have been already in the market are EPROM (Erasable and Electrically Programmable Read Only Memory) which data is written electrically and erased by ultra-violet light and EEPROM (Electrically Erasable and Programmable Read Only Memory) which data is erased and written electrically. FIG. 12 is a sectional view showing the structure of a memory cell in an EPROM. FIG. 13 is a sectional view showing the structure of a memory cell in an EEPROM.
With reference to FIG. 12, each memory cell in the EPROM includes a single FAMOS (Floating-gate Avalanche Injection MOS) transistor. The FAMOS transistor includes N type impurity regions 2 and 3 as a drain and a source formed at a P type substrate 1, a conductor layer 5 of polysilicon formed on P type substrate 1, with an oxide film 6 provided therebetween, to extend between N type impurity regions 2 and 3, and a conductor layer 4 formed on conductor layer 5 with an oxide film 7 provided therebetween. Conductor layers 4 and 5 are a control gate and a floating gate of the FAMOS transistor, respectively.
A high voltage is applied to drain 2 and control gate 4 in a data writing. As a result, a large channel current flows between drain 2 and source 3. The electric field in the channel between drain 2 and source 3 is so strong in the proximity of drain 2 that electrons in the channel are sufficiently accelerated to obtain high energy. Part of the high energy electrons (hot electrons) has higher energy than barrier energy of oxide film 6 provided between floating gate 5 and semiconductor substrate 1 in the direction of floating gate 5 due to the high potential of control gate 4. The part of the hot electrons reaching floating gate 5 are captured by the gate 5. Stop of the application of a high voltage to drain 2 and control gate 4 prevents the hot electrons from flowing to floating gate 5. With floating gate 5 being electrically insulated from control gate 4 and P type substrate 1 by insulation films 7 and 6, respectively, the potential energy of the hot electrons captured by floating gate 5 is lower than the potential energy of oxide films 6 and 7. As a result, the electrons once captured by floating gate 5 will stay there for a long time period.
Data "0" and "1" correspond to the capture of electrons by floating gate 5 and non-capture thereof, respectively.
The capture of the electrons by floating gate 5 impedes formation of an inversion layer to be generated between drain 2 and source 3. As a result, a threshold voltage of the memory cell after a data writing becomes higher than that before the data writing. Reading of the data, therefore, is executed by applying an appropriate positive voltage to control gate 4, thereby determining as to whether current flows between drain 2 and source 3. The appropriate voltage is set to be higher than a threshold voltage of an FAMOS transistor with no data written, that is, with no electron injected to floating gate 5 and lower than a threshold voltage of an FAMOS transistor with data written, that is, with electrons injected to floating gate 5. The FAMOS transistor constituting the memory cell conducts only when no electron is injected to floating gate 5, resulting in producing current flowing between drain 2 and source 3. Whether the storage data of the memory cell is "0" or "1" is determined by detecting the presence of a current flowing between source 3 and drain 2.
Such high energy ray as ultra-violet light is directed to the FAMOS transistor in a data erasing. The photoenergy of the ray excites the electrons captured by floating gate 5 to attain higher energy than the potential energies of oxide films 6 and 7. As a result, the electrons captured by floating gate 5 are discharged to control gate 4 or substrate 1.
A memory cell array of an EPROM includes FAMOS transistors each structured as shown in FIG. 12, these transistors are arranged in a matrix of rows and columns. Respective control gates 4 of all the FAMOS transistors arranged in the same row are connected to the same word line. Respective drains of all the FAMOS transistors arranged in the same column are connected to the same bit line. Voltages are applied to drains 2 and control gates 4 through the bit line and the word line. An application of a high voltage to one word line and one bit line selectively writes data "0" in a single memory cell having control gate 4 and drain 2 connected to the one word line and the one bit line, respectively. In a data erasing, the entire memory cell array is irradiated with ultra-violet ray, resulting in a total erasing made for the storage data of the whole message in the memory cell array.
With reference to FIG. 13, each memory cell of an EEPROM includes a single stacked gate transistor 10 and a single MOS transistor 11 formed on the same substrate. FAMOS transistor 10 includes N type impurity diffusion layers 2 and 3 as a source and a drain formed at a P type substrate 1, a control gate 4 and a floating gate 5. Floating gate 5 is formed on P type substrate 1 with an oxide film 6 provided therebetween to extend between drains 2 and 3. Control gate 4 is formed on floating gate 5 with an oxide film 7 provided therebetween. In this stacked gate transistor 10, oxide film 6 provided between floating gate 5 and substrate 1 has a thickness (200.ANG. or more in general) in the portion corresponding a portion between source 2 and drain 3 to prevent the tunnel phenomenon and formed to be thin (about 100.ANG. in general) in the portion corresponding to the end portion of drain 2 to cause the tunnel phenomenon. The thin portion 6b of oxide film 6 is referred to as a tunnel oxide film. On the other hand, in an stacked gate transistor (FIG. 12) for use as a memory cell in an EPROM, oxide film 6 provided between substrate 1 and floating gate 5 has an even thickness extensively (200.ANG. or more in general) to prevent the tunnel phenomenon. Data writing and erasing of the EEPROM is carried out by using the tunnel oxide film 6b.
In a data writing, a high voltage, with drain 2 as a potential side higher, is applied to the region between drain 2 and control gate 4. As a result, a high electric field of the reverse direction to that in the data writing is generated in oxide film 6b, so that the electrons of floating gate 5 tunnel through oxide film 6b to be discharged to drain 2. The electrons captured by floating gate 5 are removed therefrom. A threshold voltage of stacked gate transistor 10 with a floating gate 5 capturing electrons is higher than that of a stacked gate transistor 10 with a floating gate 5 capturing no electron as a matter of course. Data writing and data erasing for an EEPROM is also performed by changing a threshold voltage of stacked gate transistor 10 constituting each memory. Conversely, a high voltage is applied between drain 2 and control gate 4 to make control gate 4 have a higher potential in a data writing. As a result, a high electric field with floating gate 5 as a potential side higher, is generated in tunnel oxide film 6b to cause the tunnel phenomenon. That is, hot electrons generated in the proximity of drain 2 and tunnelling through oxide film 6b are injected to floating gate 5. With no high voltage applied to the region between drain 2 and control gate 4, the electrons injected to floating gate 5 will stay in floating gate 5 for a long time period as in the case of the EPROM.
Whether the storage data of the memory cell is "0" or "1" can be determined by detecting the presence of a current flowing between drain 2 and source 3 of a memory cell having control gate 4 supplied with an appropriate potential (lower than the threshold voltage of FAMOS transistor 10 having a floating gate capturing electrons and higher than the threshold voltage of FAMOS transistor 10 having a floating gate 5 not capturing electrons).
For such data erase, data write and data read done on a memory cell basis, each memory cell is provided with an MOS transistor 11. MOS transistor 11 includes an impurity diffusion layer 2 as a source which layer is formed, together with the drain of stacked gate transistor 10, at P type substrate 1, an N type impurity diffusion layer 8 as a drain formed at P type substrate 1 and a gate electrode 9 formed on P type substrate 1 to extend between impurity diffusion layers 2 and 8. Gate electrode 9 is electrically insulated from P type substrate 1 by oxide film 6.
A memory cell array of an EEPROM includes memory cells structured as shown in FIG. 13 disposed in a matrix of rows and columns, gates 9 of MOS transistors 11 constituting all of memory cells arranged in the same row being connected to the same word line and drains 8 of MOS transistors 11 constituting all of memory cells arranged in the same column being connected to the same bit line. In a data writing, a high potential is applied to control gate 4 of each of stacked gate transistors 10 and a potential equal to or higher than a threshold voltage of MOS transistor 11 and a ground potential are applied to the one word line and the one bit line, respectively. As a result, data is written only the memory cell having gate 9 and drain 8 connected to the one word line and the one bit line, respectively. In a data erasing, control gates 4 of all the stacked gate transistors 10 are grounded and a potential equal to or higher than the threshold voltage of MOS transistor 11 and a high potential are applied to one word line and one bit line, respectively. As a result, only the data of the memory cell having gate 9 and drain 8 connected to the one word line and the one bit line, respectively, is erased. In a data reading, with said appropriate potential being applied to control gates 4 of all the stacked gate transistors 10 and a potential equal to or higher than the threshold voltage of MOS transistor 11 being applied to one word line, the presence of current flowing through one bit line is detected. As a result, only the storage data is read of the memory cell having gate 9 and drain 8 respectively connected to the one word line and the one bit line.
As described above, each memory cell of an EPROM is structured by a single transistor, while each memory cell of an EEPROM is structured by two transistors. The EPROM requiring low bit cost achieves high integration density with ease, while the EEPROM requiring high bit cost does not as a result. In operation, data erasing of the EPROM is carried out by using an ultra-violet ray, while data of the EEPROM is erased electrically. As a result, the EPROM allows the total erasing of the data of all the memory cells, while the EEPROM enables selective data erasing, for example, on a byte basis.
A flash EEPROM enabling total electrical erasing of storage data of all memory cells has drawn much attention as a non-volatile semiconductor memory device other than such EPROM and EEPROM. FIG. 14 is a diagram showing the sectional structure of each memory cell in a flash EEPROM. With reference to FIG. 14, each memory cell, similar to EPROM, is structured by a single FAMOS transistor. Unlike the FAMOS transistor constituting each memory cell of the EPROM, the present FAMOS transistor, however, generally has the thickness of an oxide film 6 provided between a floating gate 5 and a P type substrate 1 set to be as small as about 100.ANG. to cause the tunnel phenomenon. In a data writing, a high voltage is applied to a control gate 4 and a drain 2 to generate hot electrons which will be injected to floating gate 5. In a data erasing, control gate 4 is grounded and source 3 is supplied with a high voltage. This causes the tunnel phenomenon between floating gate 5 and source 3 and thus electrons stored in floating gate 5 tunnel through oxide film 6 to be discharged to source 3. The film thickness of an oxide film 7 between control gate 4 and floating gate 5 is 200.ANG. or more in general to prevent tunneling.
The flash EEPROM also includes a plurality of memory cells arranged in a matrix of rows and columns, with control gates 4 of FAMOS transistors constituting the respective memory cells arranged in the same row being connected to the same word line and drains 2 of FAMOS transistors constituting the memory cells arranged in the same column being connected to the same bit line. A voltage is applied to control gate 4 and drain 2 through a word line and a bit line, respectively, in the data writing and the data erasing. In the flash EEPROM, sources 3 of the FAMOS transistors each constituting each of all the memory cells are connected to a common signal line (hereinafter referred to as a source line). In the data erasing, a high voltage is applied to the source line and all the word lines are grounded. Data erasing of the flash EEPROM is simultaneously made for all the bits as a result.
FIG. 9 is a conceptual circuit diagram showing the structure of a memory array in a flash EEPROM. For the purpose of simplicity, FIG. 9 shows a memory array including memory cells arranged in a matrix of 3 rows and 3 columns. FIGS. 10A-10D are tables showing one example of the potentials on a word line, a bit line and a source line at the time of writing data in the flash EEPROM and FIG. 11A is a table showing one example of the potentials on the word line, the bit line and the source line at the time of erasing data of the flash EEPROM. FIG. 11B is a table showing one example of the potentials on the word line, the bit line and the source line at the time of reading data of the flash EERPOM.
With reference to FIG. 9, memory cells M11, M12 and M13 in the first row each have a control gate connected to a word line WL1, memory cells M21, M22 and M23 in the second row each have a control gate connected to a word line WL2 and memory cells M31, M32 and M33 in the third row each have a control gate connected to a word line WL3. Each drain of memory cells M11, M21 and M31 in the first column is connected to a bit line BL1, each drain of memory cells M12, M22 and M32 in the second column is connected to a bit line BL2 and each drain of memory cells M13, M23 and M33 in the third column is connected to a bit line BL3. Bit lines BL1, BL2 and BL3 are connected to a node D through N channel MOS transistors Q1, Q2 and Q3, respectively. Each source of all the memory cells Mij (i=1, 2, 3:j=1, 2, 3) is connected to the same node S. Node D is supplied with a high potential and a ground potential in a data writing and a data erasing, respectively. Node S is supplied with the ground potential and a high potential in the data writing and the data erasing, respectively. Transistors Q1-Q3 are provided for selecting one of bit lines BL1-BL3 supplied with the potential of node D. Transistors Q1, Q2 and Q3 is controlled by control signals C1, C2 and C3, respectively.
For writing data in memory cell M22, for example, a logical level of control signal C2 is brought to high, while the other control signals C1 and C3 are brought to a logical low level. At the same time, a high voltage of about 12V is applied to word line WL2, while the potentials on the other word lines WL1 and WL3 are set to 0V. In other words, bit line BL2 and word line WL2 are selected. As a result, the potentials of the control gate, the drain and the source of memory cell (hereinafter referred to as a selected memory cell) M22 located at the cross-over point of the selected bit line BL2 and the selected word line WL2 become 12V, 7V and 0V, respectively, as shown in FIG. 10(A). The hot electrons generated in the proximity of the drain are injected to the floating gate, in the selected memory cell M22. The potentials of the control gate, the drain and the source of each of the other memory cells M21 and M23 connected to the selected word line WL become 12V, 0V and 0V, respectively. As a result, no hot electron to be injected to the floating gate is generated in these memory cells M21 and M23 (see FIG. 10(B)).
The potentials of the control gate, the drain and the source of each of the other memory cells M12 and M32 connected to the selected bit line BL2 become 0V, 7V and 0V, respectively, as shown in FIG. 10(C). No hot electron to be injected to the floating gate is generated in these memory cells M12 and M32. The potentials of the control gate, the drain and the source of each of memory cells M11, M13, M31 and M33 having the control gate and the drain connected to non-selected word lines and non-selected bit lines become 0V, 0V and 7V, respectively as shown in FIG. 10(D). No hot electron is generated and no hot electron is injected to the floating gate in any of memory cells M11, M13, M31 and M33. As a result, data "0" is written only in the selected memory cell M22 but not in other memory cells.
In a data erasing, all of control signals C1-C3 attain a logical high level to pull the potentials on all the bit lines BL1-BL3 to approximately 0V. As a result, the potentials of the control gate, the drain and the source of each of all the memory cells Mij become 0V, 0V and 10V, respectively, as shown in FIG. 11A. The electrons are extracted from the floating gate to the source of each of all the memory cells Mij. Although non-selected bit lines can be at a floating state, they should have a potential equal to or lower than a voltage (read voltage) to be applied to the control gate for data reading, it is set approximately 0V in practice.
In a data reading, the potential of one of control signals C1-C3 and the potential of one of word lines WL1-WL3 are brought to an ordinary potential corresponding to a high level, that is, to 5V and a lower potential of about 2V, respectively, and a ground potential are applied to nodes D and S.
For reading the data from memory cell M22, for example, a logic level of control signal C2 is brought to high, while both of the logic levels of the other control signals C1 and C3 are brought to low. At the same time, 5V is applied to word line WL2. As a result, 5V, 2V and 0V are applied to the control gate, the drain and the source of the selected memory cell M22 as shown in FIG. 11B. When the selected memory cell M22 stores data of "1", memory cell M22 is turned on to cause a current to flow from node D to node S through transistor Q2, bit line BL2 and memory cell M22. With the memory cell M22 storing data of "0", memory cell M22 remains off to cause no such current.
Out of memory cells M11-M13 and M31-M33 respectively connected to 0V word lines WL1 and WL3, the potentials of the control gate, the drain and the source of each of the two memory cells M12 and M32 connected to bit line BL2 are 5V, 2V and 0V, respectively, as show in FIG. 11C. These two memory cells M12 and M32 therefore remain OFF irrespective of their storage data. No current flows from node D to node S through either of memory cells M12 and M32.
Out of the memory cells connected to word lines WL1 and WL3, all the drains of 6 memory cells M11, M13, M21, M23, M31 and M33 connected to bit lines BL1 and BL3 are in a floating state (see FIG. 11D and 11E). Therefore, no current is generated which flows from bit line BL1 to node S irrespective of the states of memory cells M11, M21 and M31 (either in an ON state or an OFF state). Similarly, no current is generated which flows from bit line BL3 to node S irrespective of the states of the memory cells M13, M23 and M33.
Whether the current is drawn out from node D or not is determined by whether a current flowing to bit line BL2 is generated or not, that is, by the storage data of the selected memory cell M22.
A sense amplifier (not shown) detects the presence of a current extracted from node D. The detection result of the sense amplifier is taken as the storage data of memory cell M22.
As described in the foregoing, a flash EEPROM including a memory cell structured by a single transistor requires low bit cost and advantageously achieve high integration. In operation, the flash EEPROM is structured to allow the total electrical erasing to be made for the storage data of all the memory cells.
As shown in FIG. 9, a memory cell array of a flash EEPROM is constituted by a plurality of blocks in general, not by a single block. FIG. 8 is a schematic block diagram showing a typical entire structure of a flash EEPROM With reference to FIG. 8, the flash EEPROM includes, for example, a memory array 100 divided into eight blocks 101-108, source/erase circuits 110, X decoder 120, Y decoders 130 and Y gates 140, each corresponding to each of 8 blocks 101-108. The flash EEPROM further includes sense amplifier and write circuits 150 provided corresponding to 8 blocks 101-108 and input/output buffers 160 provided corresponding to sense amplifier and write circuits 150. X decoder 120 is connected to terminals A0-Am for receiving external row address signals. Y decoder 130 is connected to terminals B0-Bn for receiving external column address signals. Input/output buffers 160 are respectively connected to terminals D0-D7 for receiving write data to memory array 100 and read data from the same. In memory array 100, word lines are provided each in common for 8 blocks 101-108, while bit lines BL are provided in the same number for each of 8 blocks 101-108. Each memory cell (not shown) is provided at a cross-over point of a word line WL and a bit line BL. In memory array 100, each of 8 blocks 101-108 corresponds to one bit.
X decoder 120, in response to external row address signals from address terminals A0-Am, selects one of the word lines WL and applies a high voltage (in a data writing) of about 12V or a power source voltage of 5V (in a data reading) to the selected word line WL. X decoder 120 also applies 0V to all the word lines WL in a data erasing. Y decoder 130, in response to external column address signals from address terminals B0-Bn, outputs a signal for selecting one of the bit lines BL in each block of memory array 100. More specifically, each Y gate 140 includes one MOS transistor 180 equivalent to transistors Q1-Q3 shown in FIG. 9, for each of all the bit lines BL included in the corresponding block (one of 101-108).
Y decoder 130 supplies a gate voltage to these MOS transistors 180 in response to the external column address signals to render one of the MOS transistors 180 which are included in the respective Y gates 140 conductive and the others non-conductive. MOS transistors 180 included in each Y gate 140 are provided between the respective bit line BL included in the corresponding block in memory array 100 and the corresponding sense amplifier and write circuit 150. As a result, one of the bit lines BL in each of 8 blocks 101-108 constituting memory array 100 is electrically connected to the corresponding sense amplifier and write circuit 150 through the corresponding Y gate 140. All bit lines BL in each of blocks 101-108 are connected to source/erase circuit 110 through the same source line 170. Source/erase circuit 110 applies 0V (in a data writing and a data reading) or a high voltage of about 10V (in a data erasing) to all the source lines 170.
In a data writing, 8-bit external data is applied to data input/output terminals D0-D7. Each of data input/output terminals D0-D7 receives a data signal of any one bit of the 8-bit data. Each input/output buffer 160 buffers the data signal from the corresponding data input/output terminal (one of D0-D7) and applies the same to the corresponding sense amplifier and write circuit 150. Each sense amplifier and write circuit 150 applies a high voltage of about 7V to the corresponding Y gate 140 when the data signal from the corresponding input/output buffer 160 corresponds to the logical value of "0" and applies a low voltage of about 0V to the corresponding Y gate 140 when the data signal from the corresponding input/output buffer 160 corresponds to the logical value of "1". As a result, the external data is written only in a single memory cell in each of 8 blocks 101-108 having a control gate and a drain connected to the word line WL supplied with a high voltage by X decoder 120 and the bit line BL supplied with a high voltage by Y gate 140.
In a data reading, each sense amplifier and write circuit 150 detects the presence of a current flowing through one bit line BL electrically connected to the circuit through the corresponding Y gate 140. Each sense amplifier and write circuit 150, when it detects the current flowing through said one bit line BL, outputs a data signal equivalent to the logical value "1" to the corresponding input/output buffer 160 and when no current flowing through said one bit line BL is detected, the circuit outputs a data signal equivalent to the logical value "0" to the corresponding input/output buffer 160. Each input/output buffer 160 buffers the data signal from the corresponding sense amplifier and write circuit 150 and outputs the same to the corresponding one of data input/output terminals D0-D7.
One-bit data is simultaneously written in each of 8 blocks 101-108 constituting memory array 100 in a single data writing and 1-bit data is simultaneously read from each of the 8 blocks 101-108 in a single data reading. That is, the data writing and the data reading are carried out on a byte basis.
In a data erasing, each sense amplifier and write circuit 150 applies a low voltage of about 0V to the corresponding Y gate 140. At the same time, Y decoder 130 renders conductive all the MOS transistors 180 included in the respective Y gates 140. As a result, the storage data of all the memory cells included in all the blocks 101-108 or storage data of one block included in memory array 100 is erased in a single data erasing.
In the data writing and the data erasing, the high voltage (equal to or larger than 5V) and a normal power source voltage (5V) to be applied to the word lines, the bit lines and the source line are externally supplied to power source terminals Vpp and Vcc, respectively. In practice, a switch circuit 190 selectively supplies either of the voltages applied to power source terminals Vpp and Vcc to source/erase circuit 110, X decoder 120 and Y decoder 130. Each function portion of the flash EEPROM operates as described above in response to such external control signals as a write enable signal WE for designating a data writing mode and an erase enable signal EE for designating a data erasing mode. The external control signals are supplied to a control terminal 192.
As described in the foregoing, the storage data of all the memory cells in each block in memory array 100 is erased in a single data erasing. That is, unlike the data writing and the data reading, the data erasing is not performed on a byte basis but simultaneously for all the bits or for each of the blocks constituting memory array 100.
While the flash EEPROM with one memory cell comprising one transistor requires low bit cost and achieves high integration density, in operation, data is erased on a block basis constituting a memory array, which makes selective erase of storage data of the memory array impossible.
Conventional non-volatile semiconductor memory devices, as described above, roughly fall into an EPROM and a flash EEPROM which require low bit cost and can be highly integrated, and an EEPROM which requires high bit cost and cannot be highly integrated with ease. With a recent increase in storage capacity of a semiconductor memory device, that is, an increase in the number of memory cells included in one semiconductor memory device, there is an increasing demand for a memory cell structure requiring low bit cost and achieving higher integration with ease. The non-volatile semiconductor memory devices which are previously described have the advantage in meeting such demands. In conventional EPROM and flash EEPROM, however, data erasing is performed for all the bits at the same time or on a block basis constituting a memory array. It is therefore impossible to selectively erase storage data of one or some memory cell(s) in the memory array and rewrite the memory cells. In this respect, the EPROM and the flash EEPROM are not highly functional. On the other hand, the latter non-volatile semiconductor memory devices (EEPROM) requiring high bit cost cannot achieve higher integration with ease, while the devices are highly functional because of the data erase made on a byte basis. As described in the foregoing, none of the conventional non-volatile semiconductor memory devices has a structure which allows an increase in storage capacity and is highly functional to selectively erase storage data of an arbitrary memory cell.